1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and its programming method.
2. Description of the Related Art
Nonvolatile semiconductor memory devices with multi-valued memory cells that store more than one bit of data are currently undergoing development. Multi-valued memory can be implemented by a multi-level technique, which uses multiple threshold voltages, a multi-bit technique, in which each memory cell has multiple storage areas, or a combination of both techniques. One type of multi-bit memory cell places two physically noncontiguous silicon nitride sidewall charge traps on opposite sides of the gate electrode in each memory cell. Each charge trap stores one bit of data with a value of ‘0’ or ‘1’, depending on the amount of charge stored in the charge trap. Together, the two charge traps store two bits of data.
In its initial state, with little or no stored charge, a charge trap conventionally represents a ‘1’. To program the charge trap to the ‘0’ state, positive voltages are applied to the gate electrode and the adjacent main (source or drain) electrode while the other main electrode is grounded. If the gate voltage is sufficiently high, hot electrons are injected into the charge trap and its data value changes to ‘0’.
To read the data in the charge trap, positive voltages are applied to the gate electrode and the non-adjacent main electrode, the adjacent main electrode is grounded, and the resulting current flow is compared with a threshold current. If there is no stored charge in the charge trap, the current flow exceeds the threshold current, indicating a ‘1’. If the charge trap has been programmed, the charge of the electrons stored in the charge trap acts counter to the positive gate voltage, reducing the current flow to a value lower than the threshold current, thereby indicating a ‘0’.
Ideally ‘0’ and ‘1’ data are represented by the same current values in all memory cells, but in practice, process variations and other factors produce cell-to-cell differences that somewhat scatter the current values. The threshold for discrimination between ‘0’ and ‘1’ data must be located in a so-called current window between the range of scatter of the ‘1’ read currents and the range of scatter of ‘0’ read currents. The wider the current window is, the more reliable the discrimination between ‘0’ and ‘1’ becomes.
A two-bit memory cell of the above type is described by Ono in Japanese Patent Application (JP) No. 2005-64295. The same type of memory cell can be made to store four bits of data by programming the charge traps to four different levels of charge, representing data values of ‘0’, ‘1’, ‘2’, and ‘3’, which are read by comparing the read current with three threshold values. The memory cell is programmed as described above except that the ‘3’ state is the initial state, a first gate voltage is used to program a ‘0’, a second, lower gate voltage is used to program a ‘1’, and a third, still lower gate voltage is used to program a ‘2’.
In 4-bit per Cell NRM Reliability, Institute of Electrical and Electronics Engineers (IEEE) International Electron Devices Meeting (IEDM) Technical Digest, IEEE, 2005, Eitan et al. describe a method of programming a charge trap in this type of four-bit memory cell in large and small increments by executing a series of alternating program and verify steps. First the charge trap is programmed with preset drain and gate voltages, and the charge trap is read to verify its read current. If the read current is not yet below the corresponding threshold current, the charge trap is programmed again with a higher drain voltage or gate voltage, and then verified again. These steps are iterated until the read current is below the threshold level, at which point the procedure ends.
In JP 2008-85196, Yuda describes a method of programming a charge trap in this type of four-bit memory cell by programming its two charge traps alternately, so that each program-verify cycle in one charge trap is followed by a program-verify cycle in the other charge trap, unless the programming process in the other charge trap has already been completed. The gate voltages are selected so that the number of program-verify iterations is substantially the same for all charge traps, regardless of whether a ‘0’, ‘1’, or ‘2’ is being programmed. This limits the reduction in the read current value of a charge trap that occurs after its programming has been completed if further programming of the other charge trap in the same memory cell takes place, and ensures that current windows adequate for discrimination among the four data values are maintained.
If the read currents in the initial (‘3’ data) state are widely scattered, however, as may occur due to process variations and other factors, some memory cells may have unexpectedly high initial read current values. When these memory cells are programmed, many more than the anticipated number of program-verify cycles may be needed to reduce the read current to the necessary level.
If, for example, a ‘0’ is programmed into one charge trap in such a memory cell and a ‘2’ is programmed into the other (mirror) charge trap in the same memory cell, and if the programming of the ‘2’ ends many iterations before the programming of the ‘0’, the continuing ‘0’ program-verify cycles will then reduce the ‘2’ read current and narrow the current window, possibly causing the programmed ‘2’ to be mistakenly read as a ‘1’. In short, a large scatter in initial read current levels can lead to unreliable reading after the memory device is programmed.
Programming the two charge traps in each memory cell alternately in this way also requires many individual programming operations.
An object of the present invention is to provide a nonvolatile semiconductor memory and programming method that can reduce the number of programming operations necessary in data programming and improve the reliability with which the data are read.